Relaxed virtual memory in Armv8-A

Software Transactional Memory on Relaxed Memory Models

Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptions are often violated in realistic settings, as STM implementations run on relaxed memory models, with the atomicity of operations as provided by the hardware. This paper presents the first approach to verify STMs under relaxed...

Hiding Relaxed Memory Consistency with a Compiler

Modeling Relaxed Memory Consistency Protocols

This paper presents a modeling approach based on deterministic and stochastic Petri nets (DSPN's) for analyzing memory consistency protocols for multiprocessors with Distributed Shared Memory (DSM). DSPN's are a numerically solvable modeling formalism with a graphical representation. The modeling approach addresses in particular the performance degradation due to the amount of message exchange,...

Implementing GCM on ARMv8

The Galois/Counter Mode is an authenticated encryption scheme which is included in protocols such as TLS and IPSec. Its implementation requires multiplication over a binary finite field, an operation which is costly to implement in software. Recent processors have included instructions aimed to speed up binary polynomial multiplication, an operation which can be used to implement binary field m...

Binary field multiplication on ARMv8

In this paper, we show efficient implementations of binary field multiplication over ARMv8. We exploit an advanced 64-bit polynomial multiplication (PMULL) supported by ARMv8 and conduct multiple levels of asymptotically faster Karatsuba multiplication. Finally, our method conducts binary field multiplication within 57 clock cycles for B-251. Our proposed method on ARMv8 improves the performanc...